Testing of integrated circuit (IC) devices to ensure proper operation may include testing of I/O (input/output) buffer circuitry. For example, testing may include a test of DRAM (Dynamic Random Access Memory) I/O buffer circuitry. Testing may include testing according to U.S. patent application Ser. No. 13,625,744 entitled “Method, System, and Apparatus for Evaluation of Input/Output Buffer Circuitry”.
In such testing, there may be operations for automated test equipment (ATE) to provide certain testing operations for DRAM memory, including testing of the response of memory IO interfaces to varying signal delay.
However, testing equipment may not support test operations as needed to provide signal delay testing. In particular, older ATE may be unable to provide sufficient timing edge resolution for certain delay testing of the IO interfaces of integrated circuit devices.